Time division multiplexing is one technique used to implement a switching system. Consider a switch fabric with N input ports that each receive packets at rate R and N output ports that each transmit packets at rate R, as shown in FIG. 1. For a shared memory TDM switching system, a single memory bus is required that has an aggregate bandwidth of 2×N×R. The arriving packets are aggregated and written to the memory. Once written to memory, the packets are read out of the memory and transmitted on the output ports.
This system operates correctly and in a non-blocking fashion provided that the shared memory has enough bandwidth to service all of the input and output ports. Memory bandwidth can be increased by increasing the speed and width of the memory bus. Current memory bus speeds are technology limited to roughly 300 MHz, using microprocessor synchronous cache memories. To further increase memory bandwidth, the memory bus must be made wider.
Consider an example TDM switching system with 4 inputs and 4 outputs, as shown in FIG. 2. The input and output ports consist of 1-bit wide data paths and run at a single fixed clock rate that is the same for all ports and the memory bus. Assume that all packets are 8-bits in length. The fabric can be implemented with an 8-bit wide TDM memory bus. Over a period of 8 clock cycles, each input port is allocated one clock cycle to write a packet (8-bits) to memory and each output port is allocated one clock cycle to read a packet from memory.
There are several issues that complicate the design of TDM switching systems in practice. Depending on the application of the switching system, packets usually vary in size. Variable sized packets reduce the performance of TDM systems due to packet fragmentation on the memory bus. If a packet doesn't utilize an integral number of memory cycles, memory bandwidth is wasted on memory cycles that read or write data that is less than the memory bus width. Typically, TDM systems are implemented with a memory bandwidth greater than 2×N×R to compensate for inefficiencies due to fragmentation.
Fragmentation issues become significant as the memory width approaches, or exceeds, the minimum sized data packet. Consider a system with a memory bus width that is equal to twice the minimum packet length. During a period in which all received packets have length equal to the minimum packet length, the memory system bandwidth is reduced by 50% (or is 50% efficient), since all packets written to memory utilize only half of the memory bus data bits.
Due to packet fragmentation on the memory bus, typical TDM switching systems utilize bus widths that are at most as wide as a minimum length packet.
The total bandwidth of a shared memory TDM switching system is limited by the bandwidth of the memory bus. Memory bus bandwidth is determined by its speed (clock rate) and its width (number of bits). Given that memory speeds are fixed by the technology of available memory components, then the total bandwidth of TDM switches is limited by the minimum packet size.